`timescale 1ns / 1ns

module hex8_tb();
    reg clk;
    reg rst;
    reg [31:0] disp_data;
    wire [7:0] sel;  
    wire [7:0] seg;
    
    hex8 hex8_dut(
        .clk(clk),
        .rst(rst),
        .disp_data(disp_data),
        .sel(sel),  
        .seg(seg)  
    );
    
    initial clk = 1'b1;
    always #10 clk = ~clk;
    
    initial begin
        rst = 0;
        disp_data = 32'h00000000;
        #201;
        rst = 1;
        #2000;
        disp_data = 32'h12345678;
        #8000000;  //8ms
        disp_data = 32'h9abcdef0;
        #8000000;
        $stop;
    end
    
endmodule
